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advance information copyright ? intel corporation, 1997 may 1997 order number: 272928-003 8 x 930h x universal serial bus hub peripheral controller n usb hub with one upstream, one internal downstream, and three external downstream ports on hd/he parts or four on hf/hg parts complete universal serial bus speci- fication 1.0 compatibility serves as both usb hub and usb embedded function (internal port) n usb hub connectivity management downstream device connect/disconnect detection power management, including suspend and resume bus fault detection and recovery full and low speed downstream device support n output pin for port power switching n input pin for overcurrent detection n usb embedded function supports isochronous and non-isochronous data n on-chip usb transceivers n serial bus interface engine (sie) packet decoding/generation crc generation and checking nrzi encoding/decoding and bit-stuffing n hub fifo data buffers one pair of 16-byte transmit and receive fifos one 1-byte transmit register n embedded function fifo data buffers three pairs of 16-byte transmit and receive fifos one pair of configurable transmit and receive fifos (1 kbyte total) n automatic transmit/receive fifo management n three usb interrupt vectors endpoint transmit/receive done start of frame/hub endpoint done global suspend/resume n low clock mode n user-selectable configurations external wait state external address range page mode n real-time wait function n 256-kbyte external code/data memory space n on-chip rom options 0, 8, or 16 kbytes n 1024 bytes on-chip data ram n four input/output ports n standard mcs ? 51 uart n power-saving idle and powerdown modes n register-based mcs ? 251 architecture n code-compatible with mcs 51 and mcs 251 microcontrollers n 12-mhz crystal operation the 8 x 930h x usb hub peripheral controller is based on the mcs 251 microcontroller. it consists of standard 8xc251sx peripherals plus a usb module. the usb module provides both usb hub and usb embedded function capabilities. the 8 x 930h x supports usb hub functionality, embedded function, suspend/resume modes, isochronous/non-isochronous transfers, and it is fully usb rev 1.0 specification compliant. the usb module contains one internal and three (or four) external downstream ports and integrates the usb trans- ceivers, serial bus interface engine (sie), hub interface unit (hiu), function interface unit (fiu), and transmit/receive fifos. the 8 x 930h x uses the standard instruction set of the mcs 251 architecture, which is binary code compatible with the mcs 51 architecture.
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or oth- erwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel retains the right to make changes to specifications and product descriptions at any time, without notice. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation literature sales p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-548-4725 copyright ? intel corporation, 1997
iii contents 1.0 about this document......................................................................................................... . 1 1.1 additional information sources ...................................................................................... 1 1.2 electronic information..................................................................................................... 1 1.3 product summary........................................................................................................... 2 2.0 nomenclature overview ...................................................................................................... 4 3.0 pinout ...................................................................................................................... ............ 6 4.0 signals ..................................................................................................................... ......... 12 5.0 address map ................................................................................................................. .... 16 6.0 electrical characteristics .................................................................................................. . 17 6.1 operating frequencies................................................................................................. 17 6.2 dc characteristics........................................................................................................ 1 8 6.3 explanation of timing symbols .................................................................................... 20 6.4 system bus ac characteristics.................................................................................... 21 6.4.1 system bus timing diagrams ...............................................................................23 6.4.2 real-time wait state function ac characteristics ................................................27 6.4.3 real-time wait state function timing diagrams ..................................................28 6.5 ac characteristics synchronous mode 0 ................................................................ 30 6.6 external clock drive ..................................................................................................... 30 6.7 testing waveforms ...................................................................................................... 31 7.0 thermal characteristics .................................................................................................... 32 8.0 design considerations ...................................................................................................... 32 8.1 external bus timing and peripheral timing affected by pllsel2:0 selection ........... 32 8.2 low clock mode frequency......................................................................................... 32 8.3 setting rxffrc bit clears only the oldest packet in the fifo ................................. 32 8.4 series resistor requirement for impedance matching ................................................ 32 8.5 pullup resistor requirement for 8X930HX hub devices............................................... 32 8.6 powerdown mode cannot be invoked before usb suspend ...................................... 32 8.7 unused downstream ports........................................................................................... 33 9.0 8X930HX errata .............................................................................................................. ... 33 10.0 datasheet revision history............................................................................................... 3 3
8 x 930h x universal serial bus peripheral controller iv figures 1. 8X930HX block diagram.......................................................................................................2 2. 8X930HX usb module block diagram..................................................................................3 3. product nomenclature ......................................................................................................... 4 4. 8x930hd/he and 8x930hf/hg 68-pin plcc package.......................................................6 5. 8x930hd/he and 8x930hf/hg 64-pin sdip package ........................................................7 6. 8X930HX code fetch, nonpage mode ...............................................................................23 7. 8X930HX data read, nonpage mode ................................................................................24 8. 8X930HX data write, nonpage mode.................................................................................24 9. 8X930HX code fetch, page mode .....................................................................................25 10. 8X930HX data read, page mode ......................................................................................26 11. 8X930HX data write, page mode.......................................................................................26 12. external code fetch/data read (nonpage mode, real-time wait state) .........................28 13. external data write (nonpage mode, real-time wait state) .............................................28 14. external data read (page mode, real-time wait state) ...................................................29 15. external data write (page mode, real-time wait state) ...................................................29 16. serial port waveform synchronous mode 0..................................................................30 17. external clock drive waveforms........................................................................................30 18. ac testing input, output waveforms.................................................................................31 19. float waveforms ............................................................................................................. ...31 tables 1. related documentation........................................................................................................ 1 2. electronic information ....................................................................................................... ...1 3. description of product nomenclature...................................................................................4 5. downstream port allocation .................................................................................................5 4. proliferation options........................................................................................................ .....5 6. 68-pin plcc pin assignment...............................................................................................8 7. 64-pin sdip pin assignment ................................................................................................9 8. 68-pin plcc signal assignments arranged by functional category ................................10 9. 64-pin sdip signal assignments arranged by functional category..................................11 10. signal description .......................................................................................................... ....12 11. memory signal selections (rd1:0) ...................................................................................15 12. 8X930HX address map .......................................................................................................16 13. 8X930HX operating frequency ..........................................................................................17 14. dc characteristics at operating conditions.......................................................................18 15. ac timing symbol definitions............................................................................................20 16. ac characteristics at operating conditions.......................................................................21 17. real-time wait state ac timing specifications .................................................................27 18. serial port timing synchronous mode 0 .......................................................................30 19. external clock drive........................................................................................................ ...31 20. thermal characteristics ..................................................................................................... 32
advance information 1 8 x 930h x universal serial bus peripheral controller 1.0 about this document this data sheet contains advance information about intels 8 x 930h x universal serial bus hub peripheral controller, based on the mcs? 251 peripheral controller, which includes a functional overview, mechanical data, targeted electrical specifications (simulated), and bus functional waveforms. a detailed functional description, other than parametric performance, is published in the 8x930ax, 8X930HX universal serial bus micorcon- troller users manual (272949). 1.1 additional information sources intel documentation is available from your local intel sales representative or intel literature sales. intel corporation literature sales p.o. box 7641 mt. prospect, il 60056-7641 1-800-879-4683 1.2 electronic information we offer a variety of technical and product infor- mation through the world wide web (see table 2 for url) and through faxback service which is an on-demand publishing system that sends documents to your fax machine. you can get product announcements, change notifications, product literature, device characteristics, design recommendations, and quality and reliability infor- mation 24 hours a day, 7 days a week. just dial the telephone number and respond to the system prompts. table 1. related documentation table 2. electronic information document title order/contact 8x930ax, 8X930HX universal serial bus micorcontroller users manual intel order # 272949 universal serial bus specification intel order # 272962 document title order/contact intels world-wide web (www) location: http://www.intel.com/design/usb/ customer support (us and canada): 800-628-8686 faxback service: us and canada 800-628-2283 europe +44(0)793-496646 worldwide 916-356-3105 application bulletin board service : up to 14.4-kbaud line, worldwide 916-356-3600 dedicated 2400-baud line, worldwide 916-356-7209 europe +44(0)793-496340
2 advance information 8 x 930h x universal serial bus peripheral controller 1.3 product summary figure 1. 8 x 930h x block diagram a4340-01 src2 (8) code address (24) code bus (16) ram rom watchdog timer timer/ counters pca serial i/o port 2 drivers p2.7:0 port 0 drivers p0.7:0 port 3 drivers p3.7:0 port 1 drivers p1.7:0 data address (24) data bus (8) memory address (16) system bus and i/o ports i/o ports and peripheral signals src1 (8) ib bus (8) peripheral interface interrupt handler clock & reset bus interface instruction sequencer dst (16) alu data memory interface memory data (16) register file usb ? usb ports microcontroller core ? for details, see the usb module block diagram.
advance information 3 8 x 930h x universal serial bus peripheral controller figure 2. 8 x 930h x usb module block diagram d p3 d m3 transceiver a5102-02 d p5 d m5 d p2 d m2 d p1 d m0 d p0 d m1 repeater usb upstream port usb downstream ports serial bus interface engine (sie) transceiver transceiver transceiver hub interface unit (hiu) function interface unit (fiu) control control fifos data bus to cpu transmit/receive bus transceiver hf/hg only
4 advance information 8 x 930h x universal serial bus peripheral controller 2.0 nomenclature overview figure 3. product nomenclature table 3. description of product nomenclature parameter options description temperature and burn-in no mark commercial operating temperature range (0 o c to 70 o c) with intel standard burn-in packaging options n plastic leaded chip carrier (plcc) u shrink dual in-line package (sdip) program memory options 0 without rom 3 with rom process and voltage information no mark chmos product family 930hx advanced 8-bit microcontroller architecture with on-chip universal serial bus hub and function capability. indicates rom size, ram size, and quantity of external downstream ports (see table 4). device speed no mark 12 mhz crystal program memory options xxxxx xx x x 8 xx x packaging options temperature and burn-in options a2815-01 process information product family device speed
advance information 5 8 x 930h x universal serial bus peripheral controller table 5. downstream port allocation table 4. proliferation options 4 external downstream ports (hf/hg) 3 external downstream ports (hd/he) rom size ram size package n80930hf n80930hd 0 1024 bytes 68-pin plcc n83930hf n83930hd 8 kbytes 1024 bytes 68-pin plcc n83930hg n83930he 16 kbytes 1024 bytes 68-pin plcc u80930hf u80930hd 0 1024 bytes 64-pin sdip u83930hf u83930hd 8 kbytes 1024 bytes 64-pin sdip u83930hg u83930he 16 kbytes 1024 bytes 64-pin sdip downstream port number 8 x 930hd/he 8 x 930hf/hg 1 external external 2 external external 3 external external 4 internal (embedded function) internal (embedded function) 5 external
6 advance information 8 x 930h x universal serial bus peripheral controller 3.0 pinout figure 4 illustrates a diagram of the 8 x 930hd/he plcc package. table 6 and table 8 contain indexes of the pin arrangement. table 10 contains the signal descriptions for all pins. . figure 4. 8 x 930hd/he and 8 x 930hf/hg 68-pin plcc package upwen# ? / d p5 ? ovri# ? / d m5 ?? d p1 d m1 reserved d p0 d m0 ecap v ssp v ccp sof# d p3 d m3 reserved d p2 d m2 pllsel0 a8 / p2.0 a9 / p2.1 a10 / p2.2 a11 / p2.3 a12 / p2.4 a13 / p2.5 a14 / p2.6 a15 / p2.7 v ss v cc ea# ale psen# reserved reserved reserved ? /upwen# ?? reserved ? /ovri# ?? a4421-01 ad7 / p0.7 ad6 / p0.6 ad5 / p0.5 ad4 / p0.4 ad3 / p0.3 ad2 / p0.2 ad1 / p0.1 ad0 / p0.0 v ssp v ccp p3.0 / rxd p3.1 / txd p3.2 / int0# p3.3 / int1# p3.4 / t0 p3.5 / t1 p3.6 / wr# 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 view of component as mounted on pc board 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p3.7 / rd# / a16 p1.0 / t2 p1.1 / t2ex p1.2 / eci p1.3 / cex0 p1.4 / cex1 p1.5 / cex2 p1.6 / cex3 / wait# p1.7 / cex4 / a17 / wclk v cc v ss xtal1 xtal2 av cc rst pllsel1 pllsel2 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 note: reserved pins must be left unconnected. ? specific to the 8x930hd/he ?? specific to the 8x930hf/hg
advance information 7 8 x 930h x universal serial bus peripheral controller figure 5. 8 x 930hd/he and 8 x 930hf/hg 64-pin sdip package reserved ? / d m5 ?? av cc ad2 / p0.2 p3.3 / int1# p3.2 / int0# ad3 / p0.3 ad1 / p0.1 p3.1 / txd ad0 / p0.0 p3.0 / rxd ecap v ssp sof# v ccp dm0 pllsel0 dp0 pllsel2 dmi pllsel1 dp1 rst reserved ? / d p5 ?? xtal2 ovri# xtal1 upwen# v ss psen# v cc ale p1.7 / cex4 / a17 / wclk ea# p1.6 / cex3 / wait# v cc p1.5 / cex2 v ss p1.4 / cex1 a15 / p2.7 p1.3 / cex0 a14 / p2.6 p1.2 / eci a13 / p2.5 p1.1 / t2ex a12 / p2.4 p1.0 / t2 a11 / p2.3 p3.7 / a16 / rd# a10 / p2.2 p3.6 / wr# a9 / p2.1 p3.5 / t1 a8 / p2.0 p3.4 / t0 ad7 / p0.7 v ccp ad6 / p0.6 dp3 ad5 / p0.5 v ssp ad4 / p0.4 dm3 dp2 dm2 59 60 58 57 63 64 62 61 51 52 50 49 55 56 54 53 43 44 42 41 47 48 46 45 35 36 34 33 39 40 38 37 6 5 7 8 2 1 8X930HX a4422-01 3 4 14 15 16 10 9 11 12 22 21 23 24 18 17 19 20 30 29 31 32 26 25 27 28 note: reserved pins must be left unconnected. 56 view of component as mounted on pc board 13 ? specific to the 8x930hd/he ?? specific to the 8x930hf/hg
8 advance information 8 x 930h x universal serial bus peripheral controller table 6. 68-pin plcc pin assignment pin name pin name pin name 1v ss 24 p3.4/t0 47 reserved 2 a15/p2.7 25 p3.5/t1 48 d m 3 3 a14/p2.6 26 p3.6/wr# 49 d p 3 4 a13/p2.5 27 p3.7/rd#/a16 50 sof# 5 a12/p2.4 28 p1.0/t2 51 v ccp 6 a11/p2.3 29 p1.1/t2ex 52 v ssp 7 a10/p2.2 30 p1.2/eci 53 ecap 8 a9/p2.1 31 p1.3/cex0 54 d m 0 9 a8/p2.0 32 p1.4/cex1 55 d p 0 10 ad7/p0.7 33 p1.5/cex2 56 reserved 11 ad6/p0.6 34 p1.6/cex3/wait# 57 d m 1 12 ad5/p0.5 35 p1.7/cex4/a17/wclk 58 d p 1 13 ad4/p0.4 36 v cc 59 ovri# ? /d m5 ?? 14 ad3/p0.3 37 v ss 60 upwen# ? /d p5 ?? 15 ad2/p0.2 38 xtal1 61 reserved ? /ovri# ?? 16 ad1/p0.1 39 xtal2 62 reserved ? /upwen# ?? 17 ad0/p0.0 40 av cc 63 reserved 18 v ssp 41 rst 64 reserved 19 v ccp 42 pllsel1 65 psen# 20 p3.0/rxd 43 pllsel2 66 ale 21 p3.1/txd 44 pllsel0 67 ea# 22 p3.2/int0# 45 d m 2 68 v cc 23 p3.3/int1# 46 d p 2 ? specific to the 8 x 930hd/he ?? specific to the 8 x 930hf/hg
advance information 9 8 x 930h x universal serial bus peripheral controller table 7. 64-pin sdip pin assignment pin name pin name pin name 1v ccp 23 rst 45 ea# 2 p3.0/rxd 24 pllsel1 46 v cc 3 p3.1/txd 25 pllsel2 47 v ss 4 p3.2/int0# 26 pllsel0 48 a15/p2.7 5 p3.3/ int1# 27 dm2 49 a14/p2.6 6 p3.4/t0 28 dp2 50 a13/p2.5 7 p3.5/t1 29 dm3 51 a12/p2.4 8 p3.6/wr# 30 dp3 52 a11/p2.3 9 p3.7/a16/rd# 31 sof# 53 a10/p2.2 10 p1.0/t2 32 v ccp 54 a9/p2.1 11 p1.1/t2ex 33 v ssp 55 a8/p2.0 12 p1.2/eci 34 ecap 56 ad7/p0.7 13 p1.3/cex0 35 dm0 57 ad6/p0.6 14 p1.4/cex1 36 dp0 58 ad5/p0.5 15 p1.5/cex2 37 dm1 59 ad4/p0.4 16 p1.6/cex3/wait# 38 dp1 60 ad3/p0.3 17 p1.7/cex4/a17/wclk 39 reserved ? /d m5 ?? 61 ad2/p0.2 18 v cc 40 reserved ? /d p5 ?? 62 ad1/p0.1 19 v ss 41 ovri# 63 ad0/p0.0 20 xtal1 42 upwen# 64 v ssp 21 xtal2 43 psen# 22 avcc 44 ale ? specific to the 8 x 930hd/he ?? specific to the 8 x 930hf/hg
10 advance information 8 x 930h x universal serial bus peripheral controller table 8. 68-pin plcc signal assignments arranged by functional category address & data input/output usb name pin name pin name pin ad0/p0.0 17 p1.0/t2 28 pllsel0 44 ad1/p0.1 16 p1.1/t2ex 29 pllsel1 42 ad2/p0.2 15 p1.2/eci 30 pllsel2 43 ad3/p0.3 14 p1.3/cex0 31 d m 0 54 ad4/p0.4 13 p1.4/cex1 32 d p 0 55 ad5/p0.5 12 p1.5/cex2 33 d m 1 57 ad6/p0.6 11 p1.6/cex3/wait# 34 d p 1 58 ad7/p0.7 10 p1.7/cex4/a17/wclk 35 d m 2 45 a8/p2.0 9 p3.0/rxd 20 d p 2 46 a9/p2.1 8 p3.1/txd 21 d m 3 48 a10/p2.2 7 p3.2/int0# 22 d p 3 49 a11/p2.3 6 p3.3/int1# 23 sof# 50 a12/p2.4 5 p3.4/t0 24 ecap 53 a13/p2.5 4 p3.5/t1 25 ovri# 59 ? / 61 ?? a14/p2.6 3 p3.6/wr# 26 upwen# 60 ? / 62 ?? a15/p2.7 2 p3.7/rd#/a16 27 d m5 59 ?? p3.7/rd#/a16 27 d p5 60 ?? p1.7/cex4/a17/wclk 35 processor control power & ground bus control & status name pin name pin name pin p3.2/int0# 22 v cc 36, 68 p3.6/wr# 26 p3.3/int1# 23 v ccp 19, 51 p3.7/rd#/a16 27 rst 41 av cc 40 psen# 65 xtal1 38 v ss 1, 37 ale 66 xtal2 39 v ssp 18, 52 ea# 67 ? specific to the 8 x 930hd/he ?? specific to the 8 x 930hf/hg
advance information 11 8 x 930h x universal serial bus peripheral controller table 9. 64-pin sdip signal assignments arranged by functional category address & data input/output usb name pin name pin name pin ad0/p0.0 63 p1.0/t2 10 pllsel0 26 ad1/p0.1 62 p1.1/t2ex 11 pllsel1 24 ad2/p0.2 61 p1.2/eci 12 pllsel2 25 ad3/p0.3 60 p1.3/cex0 13 d m 0 35 ad4/p0.4 59 p1.4/cex1 14 d p 0 36 ad5/p0.5 58 p1.5/cex2 15 d m 1 37 ad6/p0.6 57 p1.6/cex3/wait# 16 d p 1 38 ad7/p0.7 56 p1.7/cex4/a17/wclk 17 d m 2 27 a8/p2.0 55 p3.0/rxd 2 d p 2 28 a9/p2.1 54 p3.1/txd 3 d m 3 29 a10/p2.2 53 p3.2/int0# 4 d p 3 30 a11/p2.3 52 p3.3/int1# 5 sof# 31 a12/p2.4 51 p3.4/t0 6 ecap 34 a13/p2.5 50 p3.5/t1 7 ovri# 41 a14/p2.6 49 p3.6/wr# 8 upwen# 42 a15/p2.7 48 p3.7/a16/rd# 9 reserved ? /d m5 ?? 39 p3.7/a16/rd# 9 reserved ? /d p5 ?? 40 p1.7/cex4/a17/wclk 17 processor control power & ground bus control & status name pin name pin name pin p3.2/int0# 4 v cc 46 p3.6/wr# 8 p3.3/int1# 5 v ccp 32 p3.7/rd#/a16 9 rst 23 av cc 22 psen# 43 xtal1 20 v ss 47 ale 44 xtal2 21 v ssp 64 ea# 45 ? specific to the 8 x 930hd/he ?? specific to the 8 x 930hf/hg
12 advance information 8 x 930h x universal serial bus peripheral controller 4.0 signals table 10. signal description (sheet 1 of 4) signal name type description alternate function a17 o address line 17. output to memory as 18th external address bit in extended bus applications. selected with bits rd1:0 in configuration byte uconfig0. see table 11 and rd#, wr#, and psen#. p1.7/cex4/wclk a16 o address line 16 . output to memory as 17th external address bit in extended bus applications. selected with bits rd1:0 in configuration byte uconfig0. see table 11 and rd#, wr#, and psen#. rd# a15:8 o address lines . upper address lines for external memory. description is for nonpage mode configuration. for page mode configuration, data (d7:0) is multiplexed with the upper address byte (a15:8). p2.7:0 ad7:0 i/o address/data lines . multiplexed lower address lines and data lines for external memory. description is for nonpage mode configuration. for page mode configuration, data (d7:0) is multiplexed with the upper address byte (a15:8). p0.7:0 ale o address latch enable . ale signals the start of an external bus cycle and indicates that valid address information is available on lines a15:8 and ad7:0. an external latch can use ale to demultiplex the address from the address/data bus. av cc pwr analog v cc . a separate v cc input for the phase-locked loop circuitry. cex2:0 cex3 cex4 i/o programmable counter array (pca) input/output pins . these are input signals for the pca capture mode and output signals for the pca compare mode and pca pwm mode. p1.5:3 p1.6/wait# p1.7/a17/wclk d m 0 , d p 0 i/o usb port 0 . d p 0 and d m 0 are the data plus and data minus lines of usb port 0, the upstream differential port. these lines do not have internal pullup resistors. provide an external 1.5 k w pullup resistor at d p 0 to indicate the connection of a fullspeed device. note: d p 0 low and d m 0 low signals an se0 (usb reset), causing the 8 x 930h x to stay in reset. d m 1 , d p 1 d m 2 , d p 2 d m 3 , d p 3 d m 5 , d p 5 i/o usb ports 1, 2, 3, and 5 . d p 1 , d p 2 , d p 3 , d m 1 , d m 2 , d m 3 , d m 5, and d p 5 are the data plus and data minus lines of usb ports 1, 2, 3, and 5, the four downstream differential ports. these lines have no internal pulldown resistors. provide an external 15 k w pulldown resistor at each of these pins. (see unused downstream ports on page 33.)
advance information 13 8 x 930h x universal serial bus peripheral controller ea# i external access . directs program memory accesses to on- chip or off-chip code memory. when ea# is connected to ground, all program memory accesses are off-chip. when ea# is connected to v cc , program accesses on-chip rom if the address is within the range of the on-chip rom; otherwise, the access is off-chip. the value of ea# is latched at reset. for devices without on-chip rom, ea# must be connected to ground. ecap i external capacitor . connect a 1 f or larger capacitor between this pin and v ss to ensure proper operation of the differential line drivers. eci i pca external clock input . external clock input to the 16-bit pca timer. p1.2 int1:0# i external interrupts 0 and 1 . these inputs set the ie1:0 interrupt flags in the tcon register. bits it1:0 in tcon select the triggering method: edge-triggered (high-to-low) or level triggered (active low). int1:0 also serves as external run control for timer1:0 when selected by gate1:0# in tcon. p3.3:2 ovri# i overcurrent sense. senses input to indicate an overcurrent condition for a bus-powered usb device on an external downstream port. active low. p0.7:0 i/o port 0 . this is an 8-bit, open-drain, bidirectional i/o port. ad7:0 p1.0 p1.1 p1.2 p1.5:3 p1.6 p1.7 i/o port 1 . this is an 8-bit, bidirectional i/o port with internal pull- ups. t2 t2ex eci cex2:0 cex3/wait# cex4/a17/wclk p2.7:0 i/o port 2 . an 8-bit, bidirectional i/o port with internal pull-ups. a15:8 p3.0 p3.1 p3.3:2 p3.5:4 p3.6 p3.7 i/o port 3 . an 8-bit, bidirectional i/o port with internal pull-ups. rxd txd int1:0# t1:0 wr# rd#/a16 pllsel2:0 i phase-locked loop select . three-bit code selects usb data rate (see table 13 on page 17). psen# o program store enable . read signal output. asserted for the memory address range determined by bits rd1:0 in configu- ration byte uconfig0 (see rd# and table 11). rd# o read. read signal output to external data memory. asserted only for rd1:0 = 11. see configuration byte uconfig0. (also see psen# and table 11). p3.7/a16 table 10. signal description (sheet 2 of 4) signal name type description alternate function
14 advance information 8 x 930h x universal serial bus peripheral controller rst i reset . reset input to the chip. holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage greater than v ih1 is applied, whether or not the oscillator is running. this pin has an internal pulldown resistor; connecting a capacitor between this pin and vcc implements power-on reset. asserting rst when the chip is in idle mode or powerdown mode returns the chip to normal operation. rxd i/o receive serial data . rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2, and 3. p3.0 sof# o start of frame . start of frame pulse. active low. asserted for 8 states (see table 13) when frame timer is locked to usb frame timing and when sof token or artificial sof is detected. t1:0 i timer 1:0 external clock input . when timer 1:0 operates as a counter, a falling edge on the t1:0 pin increments the count. p3.5:4 t2 i/o timer 2 clock input/output . for the timer 2 capture mode, this signal is the external clock input. for the clock-out mode, it is the timer 2 clock output. p1.0 t2ex i timer 2 external input . in timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. in auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. in the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. p1.1 txd o transmit serial data . txd outputs the shift clock in serial i/o mode 0 and transmits serial data in serial i/o modes 1, 2, and 3. p3.1 upwen# o usb power enable. a low signal on this pin applies power to all three external downstream ports. v cc pwr supply voltage . connect this pin to the +5v supply voltage. v ccp pwr supply voltage for i/o buffers . connect this pin to the +5v supply voltage. v ss gnd circuit ground . connect this pin to ground. v ssp gnd circuit ground for i/o buffers . connect this pin to ground. wait# i real-time wait state input. the real-time wait# input is enabled by writing a logical 1 to the wcon.0 (rtwe) bit at s:a7h. during bus cycles, the external memory system can signal system ready to the microcontroller in real time by controlling the wait# input signal on the port 1.6 input. p1.6/cex3 wclk o wait clock output. the real-time wclk output is driven at port 1.7 (wclk) by writing a logical 1 to the wcon.1 (rtwce) bit at s:a7h. when enabled, the wclk output produces a square wave signal with a period of tclk. p1.7/cex4/a17 table 10. signal description (sheet 3 of 4) signal name type description alternate function
advance information 15 8 x 930h x universal serial bus peripheral controller ? rd1:0 are bits 3:2 of configuration byte uconfig0. refer to figure 4-3 on page 4-5 in the 8x930ax, 8X930HX universal serial bus micorcontroller users manual . wr# o write. write signal output to external memory (see table 11). p3.6 xtal1 i oscillator amplifier input . when implementing the on-chip oscillator, connect the external crystal/resonator across xtal1 and xtal2. if an external clock source is used, then connect it to this pin. xtal2 o oscillator amplifier output . when implementing the on-chip oscillator, connect the external crystal/resonator across xtal1 and xtal2. if an external oscillator is used, then leave xtal2 unconnected. table 11. memory signal selections (rd1:0) ? rd1:0 a17/p1.7/ cex4/wclk a16/p3.7/rd# psen# wr# features 0 0 a17 a16 asserted for all addresses asserted for writes to all memory locations 256-kbyte external address space 0 1 p1.7/cex4/wclk a16 asserted for all addresses asserted for writes to all memory locations 128-kbyte external address space 1 0 p1.7/cex4/wclk p3.7 only asserted for all addresses asserted for writes to all memory locations 64-kbyte external address space one additional port pin 1 1 p1.7/cex4/wclk rd# asserted for addresses 7f:ffffh asserted for addresses 3 80:0000h asserted only for writes to mcs? 51 microcontroller data memory locations. compatible with mcs 51 microcontrollers. separate 64-kbyte external program and data memories. table 10. signal description (sheet 4 of 4) signal name type description alternate function
16 advance information 8 x 930h x universal serial bus peripheral controller 5.0 address map table 12. 8 x 930h x address map internal address) description notes ff:ffffh ff:4000h external memory except the top eight bytes (ff:fff8h C ff:ffffh) which are reserved for the configuration array. 1, 2, 3 ff:ffffh ff:0000h external memory or on-chip nonvolatile memory (8 kbytes ff:0000h C ff:1fffh, 16 kbytes ff:0000h C ff:3fffh). 2, 4, 5 fe:ffffh fe:0000h external memory 2 fd:ffffh 02:0000h reserved addresses 6 01:ffffh 01:0000h external memory 2 00:ffffh 00:0420h external memory 4 00:041fh 00:0080h on-chip ram 4 00:007fh 00:0020h on-chip ram 7 00:001fh 00:0000h storage for r0Cr7 of register file 8, 9 notes: 1. 18 address lines are bonded out (a15:0, a16:0, or a17:0 selected during chip configuration). 2. data in this area is accessible by indirect addressing only. 3. eight addresses at the top of all external memory maps are reserved for current and future device configuration byte information. 4. data is accessible by direct and indirect addressing. 5. devices reset into internal or external starting locations depending on the state of ea# and configura- tion byte information. see ea# signal description in table 5. see also uconfig1:0 bit definitions in the 8x930ax, 8X930HX universal serial bus micorcontroller users manual. 6. this reserved area returns unspecified values. software can execute a write to the reserved area, but nothing is actually written. 7. data is accessible by direct, indirect, and bit addressing. 8. the special function registers (sfrs) and the register file have separate internal address spaces. 9. data is accessible by direct, indirect, and register addressing.
advance information 17 8 x 930h x universal serial bus peripheral controller 6.0 electrical characteristics 6.1 operating frequencies absolute maximum ratings ? ambient temperature under bias................... C40c to +85c storage temperature .................................. C65c to +150c voltage on any pins to v ss .............................C0.5 v to +6.5 v i ol per i/o pin ................................................................. 15 ma power dissipation (1) ..................................................... 1.5 w operating conditions ? t a (ambient temperature under bias): commercial ........................................................ -0c to +70c v cc / v ccp (digital supply voltage) ................ 4.40 v to 5.25 v v ss / v ssp ............................................................................ 0 v av cc (analog supply voltage) ...................... 4.40 v to 5.25 v f osc ............................................................................. 12 mhz note: maximum power dissipation is based on package heat-transfer limitations, not device power consumption. notice: this document contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. ? warning : stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 13. 8 x 930h x operating frequency pllsel2:0 pin 43, 42, 44 (1) xtal1 frequency (f osc ) usb rate (2) internal frequency for cpu and peripherals (1/t clk ) (3) xtal1 clocks per state (t osc /state) (5) comments 110 12 mhz 12 mbps (full speed) 12 mhz (4) 1 pll on notes: 1. other pllsel x combinations are not valid. 2. the sampling rate is four times the usb rate. 3. the ac timing specification (table 16) defines the following symbol: cpu frequency = f clk = 1/t clk . 4. the 8 x 930h x cpu and peripheral frequency is 3 mhz (low clock mode) until the lc bit in pcon is cleared by user firmware. 5. when the cpu is operating in low clock mode (3 mhz), 1 state equals 4 t osc.
18 advance information 8 x 930h x universal serial bus peripheral controller 6.2 dc characteristics table 14. dc characteristics at operating conditions (sheet 1 of 2) symbol parameter min typical (1) max units test conditions v il input low voltage (except ea#) C0.5 0.2 v cc C 0.1 v v il 1 input low voltage (ea#) 0 0.2 v cc C 0.3 v v ih input high voltage (except xtal1, rst) 0.2 v cc + 0.9 v cc + 0.5 v v ih 1 input high voltage (xtal1, rst) 0.7 v cc v cc + 0.5 v v ol output low voltage (port 1, 2, 3) 0.3 0.45 1.0 vi ol = 100 a (2) (3) i ol = 1.6 ma i ol = 3.5 ma v ol 1 output low voltage (port 0, ale, psen#, sof#) 0.3 0.45 1.0 vi ol = 200 a (2) (3) i ol = 3.2 ma i ol = 7.0 ma v oh output high voltage (port 1, 2, 3, ale, psen#, sof#) v cc C 0.3 v cc C 0.7 v cc C 1.5 vi oh = C10 a (4) i oh = C30 a i oh = C60 a v oh 1 output high voltage (port 0 in external address space) v cc C 0.3 v cc C 0.7 v cc C 1.5 vi oh = C200 a (4) i oh = C3.2 ma i oh = C7.0 ma i il logical 0 input current (port 1,2,3) C150 a v in = 0.45 v i li input leakage current (port 0) 10 a 0.45 < v in < v cc i tl logical 1-to-0 transition current (port 1, 2,3) -650 a v in = 2.0 v r rst rst pulldown resistor 40 225 k w c io 10 pf f osc = 12 mhz t a = 25c i pd powerdown current normal powerdown usb suspend 25 145 75 175 a
advance information 19 8 x 930h x universal serial bus peripheral controller i dl idle mode i cc 60 ma full speed (in low clock mode) pllsel2:0 = 110 f clk = 3 mhz 110 full speed (not in low clock mode) pllsel2:0 = 110 f clk = 12 mhz i cc active current 75 ma full speed (in low clock mode) pllsel2:0 = 110 f clk = 3 mhz 170 full speed (not in low clock mode) pllsel2:0 = 110 f clk = 12 mhz note: 1. typical values are obtained using v cc = 5.0v, t a = 25c and are not guaranteed. 2. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i oh per port pin:10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1-3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test conditions, then v ol may exceed the related specification. pins are not guaran- teed to sink current greater than the listed test conditions. 3. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. in applications where capacitive load- ing exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qual- ify ale or other signals with a schmitt trigger or cmos-level input logic. 4. capacitive loading on ports 0 and 2 causes the v oh on ale and psen to drop below the v cc specifi- cation when the address lines are stabilizing. table 14. dc characteristics at operating conditions (sheet 2 of 2) symbol parameter min typical (1) max units test conditions
20 advance information 8 x 930h x universal serial bus peripheral controller 6.3 explanation of timing symbols table 15 defines the timing symbols used in tables 11 through 14 and the associated timing diagrams. they have the form t xxyy , where the character pairs represent a signal and its condition. timing symbols represent the time between two signal / condition points. table 15. ac timing symbol definitions character signal(s) a address: a17, a16, a15:8, a7:0 c wait clock (wclk), external clock (xtal1) d data in: d7:0, rxd lale q data out: d7:0, rxd r read: rd#/psen# w write: wr# xtxd ywait# character condition h high l low v valid, setup x no longer valid, hold z floating (low impedance)
advance information 21 8 x 930h x universal serial bus peripheral controller 6.4 system bus ac characteristics test conditions: capacitive load on all pins = 50 pf, rise and fall times = 10 ns, f osc = 12 mhz. table 16. ac characteristics at operating conditions (sheet 1 of 2) symbol parameter cpu frequency @ 12 mhz (m, n = 0) cpu frequency (f clk ) variable units min max t clk 1/(cpu frequency) 83.33 (typical) ns (1) (2) t lhll ale pulse width 34.66 (0.5+m)t clk C 7 ns (4) t avll address valid to ale low 21.66 (0.5+m)t clk C 20 ns (4) t llax address hold after ale low 4 4 ns t rlrh (3) rd# or psen# pulse width 73.33 (1+n)t clk C 10 ns (5) t wlwh wr# pulse width 71.33 (1+n)t clk C 12 ns (5) t llrl (3) ale low to rd# or psen# low 55 ns t lhax ale high to address hold 40.33 (1+m)t clk C 43 ns (4) t rldv (3) rd# or psen# low to valid data/instruction in 50.33 (1+n)t clk C 33 ns (5) t rhdx (3) data/instruct. hold after rd# or psen# high 00 ns t rlaz (3) rd# or psen# low to address float 00ns t rhdz 1 (3) instruct. float after psen# high 10 10 ns t rhdz 2 (3) data float after rd# or psen# high 83.33 t clk ns t rhlh 1 (3) psen# high to ale high (instruction) 10 10 ns t rhlh 2 (3) rd# or psen# high to ale high (data) 83.33 t clk ns t whlh wr# high to ale high 88.33 t clk + 5 ns t avdv 1 address (port 0) valid to valid data/instruction in 98.66 (2+m+n)t clk C 68 ns (4) (5) notes: 1. refer to table 13 for cpu frequencies versus xtal1 frequencies. 2. xtal1 frequency is 0.25% for full speed and 1.5% for low speed. 3. specifications for psen# are identical to those for rd#. 4. m = 0,1 is the extended ale state. 5. n = 0,1,2,3 is the rd#/psen#/wr# wait state.
22 advance information 8 x 930h x universal serial bus peripheral controller t avdv 2 address (port 2) valid to valid data/instruction in 118.66 (2+m+n)t clk C 48 ns (4) (5) t avdv 3 address (port 2) valid to valid instruction in 23.33 (1+n)t clk C 60 ns (5) t avrl (3) address valid to rd# or psen# low 37.33 (1+m)t clk C 46 ns (4) t avwl 1 address (port 0) valid to wr# low 37.33 (1+m)t clk C 46 ns (4) t avwl 2 address (port 2) valid to wr# low 66.33 (1+m)t clk C 17 ns (4) t whqx data hold after wr# high 28.66 0.5 t clk C 13 ns t qvwh data valid to wr# high 68.33 (1+n)t clk C15 ns (5) t whax wr# high to address hold 70.33 t clk C 13 ns table 16. ac characteristics at operating conditions (sheet 2 of 2) symbol parameter cpu frequency @ 12 mhz (m, n = 0) cpu frequency (f clk ) variable units min max notes: 1. refer to table 13 for cpu frequencies versus xtal1 frequencies. 2. xtal1 frequency is 0.25% for full speed and 1.5% for low speed. 3. specifications for psen# are identical to those for rd#. 4. m = 0,1 is the extended ale state. 5. n = 0,1,2,3 is the rd#/psen#/wr# wait state.
advance information 23 8 x 930h x universal serial bus peripheral controller 6.4.1 system bus timing diagrams figure 6. 8 x 930h x code fetch, nonpage mode ale rd#/psen# p0 a17/a16/p2 a5011-01 state 1 state 1 (next cycle) state 2 t lhll t llrl t rlrh t rlaz t llax t avll t avdv1 t avdv2 t lhax instruction in a7:0 a17/a16/a15:8 t rhdx t rhdz1 t rhlh1 t avrl t rldv ale rd#/psen# p0 a17/a16/p2 a5011-01 state 1 state 1 (next cycle) state 2 t lhll t llrl t rlrh t rlaz t llax t avll t avdv1 t avdv2 t lhax instruction in a7:0 a17/a16/a15:8 t rhdx t rhdz1 t rhlh1 t avrl t rldv
24 advance information 8 x 930h x universal serial bus peripheral controller figure 7. 8 x 930h x data read, nonpage mode figure 8. 8 x 930h x data write, nonpage mode ale rd#/psen# p0 a17/a16/p2 a5025-02 state 1 state 3 state 2 t lhll t llrl t rlrh t rlaz t llax t rldv t avdv1 t avdv2 t lhax d7:0 a7:0 a17/a16/a15:8 t rhdx t rhdz2 t rhlh2 t avrl t avll t qvwh ale wr# p0 a17/a16/p2 a5026-02 state 1 state 3 state 2 t lhll t wlwh t llax t lhax d7:0 a7:0 a17/a16/a15:8 t whlh t avwl2 t avll t avwl1 t whax t whqx
advance information 25 8 x 930h x universal serial bus peripheral controller figure 9. 8 x 930h x code fetch, page mode ale rd#/psen# p2 a17/a16/p0 a5028-02 state 1 state 2 t lhll t llrl t rlrh t rlaz t llax t avll t avdv1 t avdv2 t lhax instruction 1 in a15:8 a17/a16/a7:0 t rhdz1 t rhlh1 t avrl t rldv t rhdx instruction 2 in t avdv3 cycle 2, page hit state 1 cycle 1, page miss ? during a sequence of page hits, psen# remains low until the end of the last page hit cycle. ?
26 advance information 8 x 930h x universal serial bus peripheral controller figure 10. 8 x 930h x data read, page mode figure 11. 8 x 930h x data write, page mode ale rd#/psen# p2 a17/a16/p0 a5029-02 state 1 state 3 state 2 t lhll t llrl t rlrh t rlaz t llax t rldv t avdv1 t avdv2 t lhax d7:0 a15:8 a17/a16/a7:0 t rhdx t rhdz2 t avrl t avll t rhlh2 t qvwh ale wr# p2 a17/a16/p0 a5030-02 state 1 state 3 state 2 t lhll t wlwh t llax t lhax d7:0 a15:8 a17/a16/a7:0 t whlh t avwl2 t avll t avwl1 t whax t whqx
advance information 27 8 x 930h x universal serial bus peripheral controller 6.4.2 real-time wait state function ac characteristics table 17. real-time wait state ac timing specifications symbol parameter f clk variable (1) (2) units min typ max t clyv wclk low to wait# setup 0 0.5 t clk C 13 ns t clyx wait# hold after wclk low (w)t clk + 5 (0.5+w)t clk C 13 ns t rlyv ( 2) psen# or rd# low to wait# setup 0 0.5 t clk C 13 ns t rlyx wait# hold after psen# or rd# low (w)t clk + 5 (0.5+w)t clk C 13 ns t wlyv wr# low to wait# setup 0 0.5 t clk C 13 ns t wlyx wait# hold after wr# low (w)t clk + 5 (0.5+w)t clk C 13 ns notes: 1. w is the number of real-time wait states (0, 1, 2, ... highest possible number). 2. the real-time wait function has a critical timing for instruction reads. it is not advisable to use this fea- ture for instruction reads during page mode.
28 advance information 8 x 930h x universal serial bus peripheral controller 6.4.3 real-time wait state function timing diagrams figure 12. external code fetch/data read (nonpage mode, real-time wait state) figure 13. external data write (nonpage mode, real-time wait state) a7:0 wclk ale rd#/psen# wait# p0 p2 a15:8 a5000-02 state 1 state 2 state 3 state 1 (next cycle) t clyx min t clyv a7:0 d7:0 stretched a15:8 stretched rd#/psen# stretched t clyx max t rlyv t rlyx max t rlyx min a7:0 wclk ale wr# t wlyv wait# p0 p2 a5002-02 state 1 state 2 state 3 state 4 t clyx min t clyv d7:0 stretched a15:8 stretched wr# stretched t wlyx max t wlyx min t clyx max
advance information 29 8 x 930h x universal serial bus peripheral controller figure 14. external data read (page mode, real-time wait state) figure 15. external data write (page mode, real-time wait state) a15:8 wclk ale rd#/psen# wait# p2 p0 a7:0 a5001-02 state 1 state 2 state 3 state 1 (next cycle) t clyx min t clyv a15:8 d7:0 stretched a7:0 stretched rd#/psen# stretched t clyx max t rlyv t rlyx max t rlyx min a15:8 wclk ale wr# t wlyv wait# p2 p0 a5003-02 state 1 state 2 state 3 state 4 t clyx min t clyv d7:0 stretched a7:0 stretched wr# stretched t wlyx max t wlyx min t clyx max
30 advance information 8 x 930h x universal serial bus peripheral controller 6.5 ac characteristics synchronous mode 0 figure 16. serial port waveform synchronous mode 0 6.6 external clock drive figure 17. external clock drive waveforms table 18. serial port timing synchronous mode 0 symbol parameter min max units t xlxl serial port clock cycle time 6 t osc ns t qvxh output data setup to clock rising edge 5 t osc C 133 ns t xhqx output data hold after clock rising edge t osc C 50 ns t xhdx input data hold after clock rising edge 0 ns t xhdv clock rising edge to input data valid 5 t osc C 133 ns valid valid valid valid valid valid valid valid rxd (in) rxd (out) txd 01 2 3 4 5 6 7 t qvxh t xlxl t xhdx t xhqx t xhdv a2592-02 set ti ? set ri ? ? ti and ri are set during s1p1 of the peripheral cycle following the shift of the eighth bit. 0.7 v cc a4119-01 0.45 v v cc C 0.5 0.2 v cc C 0.1 t chcl t clcx t clcl t clch t chcx
advance information 31 8 x 930h x universal serial bus peripheral controller table 19. external clock drive 6.7 testing waveforms figure 18. ac testing input, output waveforms figure 19. float waveforms symbol parameter min max units 1/t osc oscillator frequency (f osc )6 12mhz t chcx high time 0.35 t osc 0.65 t osc ns t clcx low time 0.35 t osc 0.65 t osc ns t clch rise time 10 ns t chcl fall time 10 ns ac inputs during testing are driven at v cc C 0.5v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at 0.45 v inputs outputs a4118-01 v ih min v ol max v cc C 0.5 0.2 v cc + 0.9 0.2 v cc C 0.1 a min of v ih for a logic 1 and v ol for a logic 0. v load + 0.1 v v load C 0.1 v timing reference points v load v oh C 0.1 v v ol + 0.1 v for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol / i oh = 20 ma. a4117-01
32 advance information 8 x 930h x universal serial bus peripheral controller 7.0 thermal characteristics the microcontroller operates over the commercial temperature range from 0 o c to 70 o c. all thermal impedance data (see table 20) is approximate for static air conditions at 1 watt of power dissipation. values change depending on operating conditions and application requirements. the intel packaging handbook (order number 240800) describes intels thermal impedance test methodology. the components quality and reliability handbook (order number 210997) provides quality and reliability information. 8.0 design considerations 8.1 external bus timing and peripheral timing affected by pllsel2:0 selection pllsel2 (pin 43), pllsel1 (pin 42), and pllsel0 (pin 44) determine the 8 x 930h x internal cpu operating frequency. see table 13. operate the 8 x 930h x at full speed by setting pllsel2:0 to 110. this provides an internal clock frequency of 12 mhz (f clk = f osc ) and sets the microcontroller state time equal to one oscillator period (t osc ). the cpu operating frequency influences the timing of all on-chip peripherals. refer to the 8x930ax , 8x930h x universal serial bus microcontroller users manual for peripheral timing formulas (refer to table 1 on page 1 for ordering information). 8.2 low clock mode frequency the internal clock f clk distributed to the cpu and peripherals is 3 mhz. peripheral timing and external bus accesses (including instruction fetch and data read/write) are affected. refer to table 13 for clock rates. 8.3 setting rxffrc bit clears only the oldest packet in the fifo if the receive fifo is set as a dual packet mode, then it can receive two packets. setting rxffrc (in rxcon registers) to indicate fifo read complete will not flush the entire fifo; it will flush only the oldest packet. the read marker will be advanced to the location of the read pointer. 8.4 series resistor requirement for impedance matching per usb rev. 1.0 specification (page 111, section 7.1.1.1), the impedance of the differential driver must be between 29 w and 44 w . to match the cable impedance, a series resistor of 27 w to 33 w should be connected to each usb line; i.e., on d p 0 (pin 55) and on d m 0 (pin 54). if the usb line is improperly terminated or not matched, then signal fidelity will suffer. this condition can be seen on the oscillo- scopes as excessive overshoot and undershoot. this condition can potentially introduce bit errors. 8.5 pullup resistor requirement for 8 x 930h x hub devices the usb specification requires a pullup resistor to allow the host to identify which devices are low speed and which are full speed in order to commu- nicate at the appropriate data rate. for 8 x 930h x hub devices (12 mbps), use a 1.5k w pullup resistor (to 3.0 v C 3.6 v) on the d p 0 line. 8.6 powerdown mode cannot be invoked before usb suspend if the 8 x 930h x is put into powerdown mode before receiving a usb suspend signal from the host, then a usb resume will not properly wake up the 8 x 930h x from powerdown model. table 20. thermal characteristics package type q ja q jc 68-pin plcc n/a n/a
advance information 33 8 x 930h x universal serial bus peripheral controller 8.7 unused downstream ports if the usb downstream ports are not used, it is still required that the two data lines be pulled low externally (similar to a disconnect) so that the inputs are not floating. this will eliminate the possibility of induced system noise. when migrating from the 8 x 930hd/he (3 external downstream port device) to the 8 x 930hf/hg (4 external downstream port device), and the additional usb port is not being used in the application, d m5 and d p5 will still require 15k external pulldown resistors. do not leave the unused port disconnected. 9.0 8 x 930h x errata the 8 x 930h x may contain design defects or errors known as errata. characterized errata that may cause the 8 x 930h x s operational behavior to deviate from published specifications are documented in a specification update (order number 272962). specification updates can be obtained from your local intel sales office or from the world wide web ( www.intel.com ). 10.0 datasheet revision history datasheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finalizing a design or ordering devices. this (-003) revision of the 8 x 930h x datasheet replaces earlier product information. the following changes were made in this revision: 1. added the 8 x 930hf/hg 4 external downstream port device.

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